"Semiconductor Thermal Packaging - the Moving Frontier"

Revolutionary and evolutionary advances in thermal packaging technology have underpinned the continuous improvement in the performance, packaging density, and reliability achieved in solid state electronic products. Rising chip heat fluxes and packaging density, driven by Moore’s Law, have necessitated ever more aggressive cooling techniques, capable of reducing the junction-to-ambient thermal resistance, while meeting the cost, volume, and weight constraints appropriate to each class of electronic equipment. As these needs have escalated, attention has shifted from the external packaging levels towards the module and board level, then the package level, and is today focused on heat removal at the chip level. Current trends suggest that on-chip hot spots will drive the choice of future thermal packaging technology. Applicable thermal management techniques and their potential for hot spot remediation, including thermoelectric microcoolers, anisotropic spreaders/TIMs, and direct cooling with dielectric liquids through thin film evaporation or pool boiling, will be considered.The meeting will be held at Qimonda at 6000 Technology Blvd., Sandston, VA at 5:30 PM. Guests should register at www.ieee.org/richmond.